It is necessary for integrated circuits (ICs), including programmable logic device (PLDs), to communicate according to established protocols. For example, when two or more ICs drive a single bit of a bus, only one IC can be allowed to provide the signal at a given time. If a single bus line is driven both high and low at the same time, then the line may assume an intermediate state, thereby producing both unpredictable logical results and an undesirable power drain at the signal destination. Further, if a data signal and a clock signal are both provided from a first IC to a second IC, the two signals must be provided at known relative times, to avoid latching the wrong data.
To avoid such situations, and to allow ICs from various manufacturers to communicate with each other, various standards have been developed specifying required input/output behavior at IC pins. Systems employing such a standard typically can include only devices adhering to the standard. Therefore, the ability to meet such a standard is a strong commercial advantage.
One such standard is the PCI standard. PCI is an open, non-proprietary local bus standard offering high performance for multiple peripheral devices. The standard is becoming widely accepted throughout the computer industry. A complete PCI Revision 2.2 specification is available from PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214, and is incorporated herein by reference. PCI works as a processor-independent bridge between a CPU and high-speed peripherals and allows PCI cards built today to be used in many different systems. In essence, the PCI standard specifies a standard data bus width, address bus width, and control signals to control a standardized set of commands implemented by the standard, e.g., read, write, and so forth. Also specified are the required timing relationships among all of these signals.
FIG. 1 shows a small part of a known circuit implementing the PCI standard (a "PCI circuit"). As shown in FIG. 1, the control signals for the PCI circuit include a tristate signal T for tristatable output buffers OBUF, as well as a data input signal I, a clock signal CK, and a Clock Enable signal PCI_CE for output registers OUTFF in which the output data is stored. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals. In the figures, input/output structures are shown as boxes including "X"s. These boxes represent buffered input/output pads such as are well known in the art.) A maximum data bus width of 64 bits mandates provision for 64 data input signals I, 64 data output registers OUTFF, and 64 data output buffers OBUF. Clock enable signal PCI_CE is not supplied at an input pad; instead it is internally generated from two externally supplied signals specified by the PCI standard: initiator ready (I.sub.RDY) and target ready (T.sub.RDY). The logical and timing interrelationships between signals I.sub.RDY and T.sub.RDY are dictated by the PCI standard. A PCI circuit also includes other signals (not shown) requiring additional input/output pads, buffers, output registers and other circuitry. Some of the additional output registers are also driven by clock enable signal PCI_CE.
The PCI standard supports two different rates of data transfer, 33 MHz (megahertz) and 66 MHz, and two different data bus widths, 32 bits and 64 bits. (The data bus width of 32 or 64 bits is typically used to identify the specific standard, although the bus implemented by the standard includes additional control signals and is therefore wider than the numerical designator.) Even the 33 MHz data rate is difficult to achieve with a 64-bit data bus, and the 66 MHz data rate is available in very few available devices at this writing. The standard is even more difficult to meet when attempting to implement a PCI circuit in a programmable logic device (PLD) such as a field programmable gate array (FPGA). A difficult requirement to meet for the 66 MHz/64-bit standard is a 6 ns (nanosecond) maximum allowable clock-to-out delay for the output register. In other words, the delay from the time the clock signal CK is available at the clock input pad to the time the output signal appears on the output pad O can be no more than 6 ns. In order to meet this timing requirement, the output register OUTFF must be located at or near the output pad O. Even so, typically several nanoseconds are consumed between the output register and the output pad. In one PLD, the Virtex.TM. device from Xilinx, Inc., the data transfer from output register to output pad requires 3 ns. Therefore, only 3 ns are available to provide the clock signal CK from the clock input pad to the output register. This timing is normally achievable using known methods (e.g., global clock networks).
However, the clock enable signal PCI_CE must be present at the output register OUTFF prior to the arrival of the clock CK. Therefore, the clock enable signal PCI_CE has less than 3 ns to reach the output register. Fortunately, the I.sub.RDY and T.sub.RDY signals have a setup time of 3 ns at the input pads. Therefore, there is a total of less than 6 ns available between the arrival of I.sub.RDY and T.sub.RDY at the input pads and the PCI_CE signal arriving at the output register.
As previously described (and as shown in FIG. 1), the clock enable signal PCI_CE does not come directly from a buffered pad. Instead, the clock enable signal is generated on-chip from the two signals I.sub.RDY and T.sub.RDY. Therefore, some internal logic ("CE Logic" in FIG. 1) is of necessity included in the clock enable path. Further, the clock enable signal PCI_CE is very heavily loaded. The PCI standard for the 64-bit bus specifies 64 data output registers driven by this signal, and there are typically several other output registers driven by PCI_CE (e.g., 13) required to implement the standard in the FPGA. Therefore, the clock enable signal PCI_CE has a fanout of more than 64. Consequently, the 3 ns I.sub.RDY and T.sub.RDY setup requirement is very difficult to meet. In particular, this requirement is difficult to meet when implementing the 64-bit, 66 MHz PCI standard in programmable logic devices, using the available programmable logic resources.
It is desirable to provide a structure and method for supplying a PCI clock enable signal from the signals I.sub.RDY and T.sub.RDY to the clock enable pins of output registers in less than the time specified by the PCI standard. It is yet further desirable to provide a similar structure and method for use in PLDs adhering to other standards.